MEMS relays as logic gates. Really?

Posted by Mattan Kamon

Even if I didn't say it, that is what I was thinking when I was approached after a talk I gave at the International Solid State Circuits Conference (ISSCC) in the "Fusion of MEMS and Circuits" session last month. The person who approached me was Matthew Spencer, a contributor on a program to use MEMS relays to realize ultra-low-power VLSI circuits [1,2,3]. He was excited about the possibilities of what our new product, MEMS+, could do for him. What exactly are they trying to do with these MEMS switches and logic? What could I have said in my talk to inspire this interest? Was his excitement warranted? I'll try to answer that in the rest of this post.

What are they trying to do for VLSI?

Matt sent me their papers after I returned from the conference [1,2,3]. And the answer to my title question is "Really!". The work is impressive and is the result of a combined effort at UC Berkeley, MIT, and UCLA. Just as MEMS RF-switches have advantages in high isolation and low insertion loss over solid-state devices, MEMS as logic gates have zero leakage in the off-state and high on-state current compared to other CMOS alternatives for ultra-low-power [1]. The device is a switch plate with a folded flexure design as shown here (posted with permission from the authors):

The switch closes at around a 10 volt gate-to-body voltage difference and closes in about 100 ns. These gates can then be assembled into circuits to create logic functions such as part of an adder that generates the carry bit (posted with permission from the authors):

A and B are, say, the 4's digit from two binary numbers. Cin is any "carry" from adding the 2's digit. Cout is the carry digit to be sent to the 8's digit. The above example demonstrates a VLSI logic function but in order to create a VLSI logic application, the logic must communicate, and for this the authors demonstrate using the switches for I/O and analog-to-digital/digital-to-analog conversion.

What did I say in my talk that could help this effort?

They hope to design logic circuits with 10's to 100's of these gates in the near term. That design process requires simulation, and to simulate these large circuits they need a good model of their switch within their circuit environment of choice, in this case Cadence Virtuoso. Matt had been tasked with creating this model, and over the past year he's gone through quite an "ordeal", as Matt put it, to create a model in Verilog-A. It doesn't model all the physics he'd like and its robustness is suspect but it does allow them to simulate a handful of switches in a minute or so of simulation.

My talk suggested a possible route for Matt to end his ordeal. The first few slides of my talk at the ISSCC conference described the larger vision for MEMS+ as a shared platform for MEMS and IC that integrates into IC and system level design flows. However, as the rest of my talk described, what we've executed most rigorously in this first release of MEMS+ is the straightforward manner of creating a circuit-level model directly from a physical description of the device. The approach relies on hints during design entry of the MEMS device that indicate the physical behavior of that section of the device. One is effectively creating a 3D schematic. The procedure is detailed in the MEMS+ video tutorial on our website. Since MEMS+ goes directly from description to model without lengthy finite-element analysis, the models can be made parametric with respect to design variables so a designer can easily explore changing dimensions or environmental conditions, such as temperature, without recreating the model.

Was the interest warranted?

I was intrigued with this new application for MEMS and MEMS+ and wanted to see just how quickly I could put together something useful with this new tool we in Coventor R&D have worked so hard to create. Given just the papers, which lacked many of the dimensions and material properties, I put together the following quick-and-dirty 3-D schematic of their design in somewhere between 1 and 2 hours of my time:

 

that time was spent reviewing the papers and mapping that to the appropriate components and design dimensions. Note I carefully made it parametric with respect to the design dimensions such as gate size and drain width so that one could explore changing those dimensions from within the circuit simulation environment. Also note that the electrical interface was carefully defined for the eventual simulation model.

I then imported the model into a the Cadence Virtuoso Library Manager (a 5 minute process), placed an instance of the new symbol, built a little test harness of voltage sources and got my first simulation in about 15 minutes of my time:

Above you see the rather boring square symbol for the switch with the 6 electrical pins exposed from the MEMS+ 3D-view (the 7th pin at the top is a mechanical pin for the z position of the gate). Inset below the symbol are some of the properties of the instance. Notice those were automatically created to give access to the MEMS+ 3D-view's design dimensions. Matt had indicated he had his own contact resistance model, so I put a 1K resistor between the contacts and turned off our own contact resistance model. I also put a 1K resistor at the source so there would be a non-floating voltage to measure (not really necessary in retrospect). I swept the gate voltage and observed contact at around 7 volts (not shown). This doesn't match the paper's value of 10 volts, but is good enough (don't forget I didn't know many of the dimensions (something I will leave Matt to do)).

The figure on the right shows a transient simulation for one on/off cycle of 10 volts applied to the gate. This shows the position of the gate over time. You can see around 10us the gate closed, but bounced a number of times before settling. It first made contact at 400 ns, which is in the right ballpark from the paper (100 ns). The simulation took a handful of CPU seconds (maybe 30, I don't quite remember).

Are we done? No. The above model would be good for MEMS design studies. For instance, I could run parameter sweeps on the design dimensions to understand how to optimize the dimensions to get greater contact force or faster switching times. However, the goal here is to simulate many of these switches together, so we'd like to optimize this model for speed at the expense of some of the details such as the bouncing. Matt even indicated that bouncing isn't an issue for them at the moment.

To that end, I spent about 2 or 3 hours tinkering with some of the knobs we provide to trade accuracy for speed. For instance, the switch's gate in the above simulation could move in all 3 translation directions (x,y,z) as well as rotate about the 3 axes. For this study, we don't need to tax the simulator by tracking the motion of all 6 degrees of freedom, so I fixed the plate to only move in z. By doing so, we also know that the gap between gate and body is uniform and so the electrostatic computation need only account for the holes and edges, not a non-uniform gap. I also added a custom contact damper to absorb the bouncing since much of the time spent was in resolving the many bounces:

Which gave the following:

The entire simulation shown took only 0.230 CPU seconds. And this is on a Linux Dell Precision 380 (circa 2005). Some more recent desktop hardware is about 4x faster. The far-right plot shows that once contact was made, the switch between drain and source was closed and the voltage at the source jumped as desired. (The astute observer will notice that the source voltage output is not 10 volts. I was getting significant parasitic actuation between the drain and the floating contact dimple so I lowered the drain voltage for this demo. Of course that force is actually there but I must have guessed contact dimples that were too large. Again, something for Matt to get right).

With a functional logic gate, we are ready to connect these together to build a logic circuit.

The voltage sources and source resistor were removed from the schematic above to create a cell-view for a single logic gate with gate, source, drain, and body terminals. The cell instances were then placed to create the carry generation circuit shown before:

Which, in 3 CPU seconds, on circa 2005 desktop hardware, generates a good carry bit for all the input combinations:

Conclusion

The above showed that with about 7 hours of work, a model capturing the fundamental electromechanical behavior of this switch could be created directly from design parameters and then tweaked for simulation speed within the Cadence Virtuoso environment. Multiple instances of this model could be assembled to simulate a small logic circuit in a few seconds with the Cadence Spectre simulator.

Many of the dimensions were guessed, however the part that made this an "ordeal" for Matt within Verilog-A is clearly not an ordeal for MEMS+.

Much could still be done from here. Obviously the design dimensions must be entered correctly. From that, a useable layout pCell could be created automatically. In addition, other features could be modeled to make this more accurate, such as nonlinear damping, stiction force, and parasitic actuation due to the drain-to-gate voltage.

Nombre: Lenny D. Ramirez C.
Asignatura: CRF
Dirección: http://info.coventor.com/memsahead/bid/36459/MEMS-relays-as-logic-gates-ReallyVer blogg: http://lennyramirez-crf2.blogspot.com/